vlsilab, uec, phamck, riscv
042-443-5165

   



Ronaldo Serrano


電気通信大学

職務: Researcher

職務: 1996

Eメール: ronaldo@vlsilab.ee.uec.ac.jp

電話番号: +8108043285598

教育

Apr 2014 - Mar 2020 : Bachelor degree, Electronics Engineering

School of Electrical, Electronic and Telecomunications, Universidad Industrial de Santander (UIS), Bucaramanga, Santander, Colombia. 

Advisor: Dr. Ckristian Duran , Co-Advisor: Dr. Elkim Roa

Dec 2020 - Mar 2023 : Doctoral degree, Doctor of Engineering

Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo, Japan. 

Advisor: Dr. Cong-Kha Pham

程度

B.Sc. Degree on Electronics Engineering

Ph.D Degree on Electronics Engineering

職歴

Jan 2018 - March 2020 - Junior Research Assistant at Research group on integrated systems OnChip - UIS

Provide support in developing and implementing an SoC generator based on a 32-bit RISC-V processor in TSMC 0.18um CMOS technology.

Apr 2020 - November 2020 - Electronic Development Engineer at Solenium S.A.S

Development of systems to measure the quality of electric energy, thermal efficiency, solar tracking control, and communications for IoT applications.

Dec 2020 - March 2023 - Research Assistant at Pham Laboratory - UEC

Provide support in developing and implementing hardware for security strategies in a Trusted Execution Environment (TEE) based on RISC-V processors.

研究内容
  • True Random Number Generators
  • Physical Unclonable Functions
  • Cryptography
  • Low-power Systems
出版物
  • R. Serrano, et al., "A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore," 2022 19th International SoC Design Conference (ISOCC), pp. 79-80, doi: 10.1109/ISOCC56007.2022.10031398. (Best Paper Cadence Award)
  • T. -K. Dang, R. Serrano et al., "A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators," 2022 19th International SoC Design Conference (ISOCC), pp. 87-88, doi: 10.1109/ISOCC56007.2022.10031300.
  • R. Serrano et al., ”A Unified NVRAM and TRNG in Standard CMOS Technology,” in IEEE Access, vol. 10, pp. 79213-79221, 2022, doi:10.1109/ACCESS.2022.3193639.
  • R. Serrano et al., ”A Unified PUF and Crypto Core Exploiting the Metastability in Latches,” in Future Internet, vol. 14, no. 298, 2022, doi:10.3390/fi14100298.
  • R. Serrano et al., ”ChaCha20–Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3,” in Cryptography, vol. 6, no. 30, 2022, doi:10.3390/cryptography6020030.
  • R. Serrano et al., ”A Robust and Healthy Against PVT Variations TRNG based on Frequency Collapse,” in IEEE Access, vol. 10, pp. 41852-41862, 2022, doi: 10.1109/ACCESS.2022.3167690.
  • T. -T. Hoang, C. Duran, R. Serrano et al., ”Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling,” in IEEE Access, doi: 10.1109/ACCESS.2022.3169767.
  • M. Sarmiento, K-D. Nguyen, C. Duran, R. Serrano et al., ”Systems on a Chip with 8bits and 32bits Processors in 0.18µm Technology for IoT Applications,” in IEEE Transactions on Circuits and Systems II: Express Briefs, early access, 2022, doi: 10.1109/TCSII.2022.3161494.
  • R. Serrano et al., ”A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications,” 2021 18th International SoC Design Conference (ISOCC), 2021, pp. 375-376, doi: 10.1109/ISOCC53507.2021.9613880. (Best Paper MetaCNI Award)
  • R. Serrano et al., ”ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3,” 2021 18th International SoC Design Conference (ISOCC), 2021, pp. 17-18, doi: 10.1109/ISOCC53507.2021.9614016.
  • R. Serrano et al., ”A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse,” in IEEE Access, vol. 9, pp. 105748-105755, 2021, doi: 10.1109/ACCESS.2021.3099534.
  • T. -T. Hoang, C. Duran, R. Serrano et al., ”System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture,” 2021 IEEE Hot Chips 33 Symposium (HCS), 2021, pp. 1-16, doi: 10.1109/HCS52781.2021.9566862.
  • M. Sarmiento, K-D. Nguyen, C. Duran, T, Hoang, R. Serrano et al., ”A Sub-µW ReversedBody-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3182-3186, Sept.
    2021, doi: 10.1109/TCSII.2021.3090102.