vlsilab, uec, phamck, riscv
研究室紹介OPAL-RING 範 研究室
042-443-5165

   

学術雑誌

  1. ホーム
  2. 学術雑誌

学術雑誌

学術雑誌

  1. Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzuki and Cong-Kha Pham: Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks, IEEE Access, 9, 24768-24786, (2021).IEEE
  2. Trong-Thuc Hoang, Ckristian Duran, Duc-Thinh Nguyen-Hoang, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzuki and Cong-Kha Pham: Quick Boot of Trusted Execution Environment With Hardware Accelerators, IEEE Access, 8, 74015-74023, (2020).IEEE
  3. Trong-Thuc Hoang, Ckristian Duran, Khai-Duy Nguyen, Tuan-Kiet Dang, Quynh Nguyen Quang Nhu, Phuc Hong Than, Xuan-Tu Tran, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki and Cong-Kha Pham: Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB), IEICE Electronics Express, 17, 20, 1-6, (2020).J-STAGE
  4. Trong-Thuc Hoang, Xuan-Thuan Nguyen, Duc-Hung Le and Cong-Kha Pham: Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias, IEEE Trans. Circuits and Systems II: Express Briefs, 66, 10, 1723-1727, (2019).IEEE
  5. Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue and Cong-Kha Pham: An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA, IEEE Trans. Circuits and Systems II: Express Briefs, 66, 3, 472-476, (2018).IEEE
  6. Hong-Thu Nguyen, Xuan-Thuan Nguyen and Cong-Kha Pham: A Low-Power Hybrid Adaptive CORDIC, IEEE Trans. Circuits and Systems II: Express Briefs, 65, 4, 496-500, (2018).IEEE
  7. Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue and Cong-Kha Pham: An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation, IEEE Access, 6, 16046-16059, (2018).IEEE
  8. Hong-Thu Nguyen, Xuan-Thuan Nguyen and Cong-Kha Pham: A High-Throughput Low-Energy Arithmetic Processor, IEICE Transactions on Electronics, E101.C, 4, 281-284, (2018).J-STAGE
  9. Katsumi Inoue, Trong-Thuc Hoang, and Cong-Kha Pham: Frequent items counter based on binary decoders, IEICE Electronics Express, 15, 20, 1-12, (2018).J-STAGE
  10. Trong-Thuc Hoang, Duc-Hung Le and Cong-Kha Pham: Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC, IEICE Electronics Express, 15, 10, 1-12, (2018).J-STAGE
  11. Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, and Cong-Kha Pham: A CORDIC-based QR decomposition for MIMO signal detector, IEICE Electronics Express, 15, 6, 1-8, (2018).J-STAGE
  12. Hong-Thu Nguyen, Xuan-Thuan Nguyen, and Cong-Kha Pham: A Low-Latency Parallel Pipeline CORDIC, IEICE Transactions on Electronics, E100.C, 4, 391-398, (2018).J-STAGE
  13. Katsumi Inoue and Cong-Kha Pham: The Memorism Processor: Towards a Memory-Based Artificially Intelligence Complementing the von Neumann Architecture, SICE Journal of Control, Measurement, and System Integration, 10, 6, 544-550, (2017).CiNii
  14. Xuan-Thuan Nguyen, Hong-Thu Nguyen and Cong-Kha Pham: An FPGA approach for high-performance multi-match priority encoder, IEICE Electronics Express, 13, 13, 1-9, (2016).J-STAGE
  15. Xuan-Thuan Nguyen, Hong-Thu Nguyen and Cong-Kha Pham: An FPGA Approach for Fast Bitmap Indexing, IEICE Electronics Express, 13, 4, 1-9, (2016).J-STAGE
  16. Trong-Thuc HOANG, Xuan-Vy LUU, Hong-Kiet SU, Duc-Hung LE, Hieu-Binh NGUYEN, Hong-Thang NGUYEN, Huu-Thuan HUYNH, Trong-Tu BUI, Quan VU and Cong-Kha Pham: Design of Co-Processor for Real-Time HMM-Based Text-to-Speech on Hardware System Applied to Vietnamese, IEICE Electronics Express, 12, 14, 1-10 (2015).J-STAGE
  17. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi and Cong-Kha Pham: A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode, IEICE Trans. Electronics, E98-C, 7, 536-543 (2015).J-STAGE
  18. Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, Duc-Hung Le and Cong-Kha Pham: Low-resource low-latency hybrid adaptive CORDIC with floating-point precision, IEICE Electronics Express, 12, 9, 1-12 (2015).J-STAGE
  19. Duc-Hung Le, Katsumi Inoue and Cong-Kha Pham: A CAM-based Information Detection Hardware System for Fast Image Matching on FPGA Volume and Number: IEICE Trans. Electronics, E97-C, 1, 65-76 (2014).J-STAGE
  20. Xuan-Thuan NGUYEN, Trong-Tu BUI, Huu-Thuan HUYNH, Cong-Kha Pham and Duc-Hung LE: An ASIC Implementation of 16-Bit Fixed-Point Digital Signal Processor, Journal of Science and Technology, 51, 4B, 282-289 (2013).ResearchGate
  21. Duc-Hung Le, Katsumi Inoue and Cong-Kha Pham: Design a Fast CAM-based Exact Pattern Matching System on FPGA and 0.18um CMOS process, IEICE Trans. Fundamentals, E96-A, 9, 1883-1888 (2013).
  22. Duc-Hung Le, Katsumi Inoue, Masahiro Sowa and Cong-Kha Pham: An FPGA-based Information Detection Hardware System Employing Multi-Match Content Addressable Memory, IEICE Trans. Fundamentals, E95-A, 10, 1708-1717 (2012).J-STAGE
  23. Van-Phuc Hoang and Cong-Kha Pham: Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications, IEICE Trans. Fundamentals, E96-A, 2, 584-590 (2013).J-STAGE
  24. Van-Phuc Hoang and Cong-Kha Pham: An Improved Hybrid LUT-based Architecture for Low-Error and Efficient Fixed-Width Squarer, IEICE Trans. Fundamentals, E95-A, 7, 1180-1184 (2012).CiNii
  25. Van-Phuc Hoang and Cong-Kha Pham: Efficient LUT-Based Truncated Multiplier and its application in RGB to YCbCr Color Space Conversion, IEICE Trans. Fundamentals, E95.A, 6, 999-1006 (2012).J-STAGE
  26. Van-Phuc Hoang and Cong-Kha Pham: An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer, IEICE Trans. Fundamentals, E94.A, 3, 995-998 (2011).J-STAGE
  27. Heng Socheat and Cong-Kha Pham: A Low-Power High-PSRR Low-Dropout Regulator with Bulk-Gate Controlled Circuit, IEEE Trans. Circuits and Systems II: Express Briefs, 57, 4, 245-249 (2010).IEEE
  28. 柴田公男, 範 公可: 高速ソフトスタート制御回路を用いた電流モードDC-DCコンバータ,電子情報通信学会A論文誌, J93-A, 2, 127-135 (2010).CiNii
  29. 柴田公男, 範 公可: 電流モードDC-DCコンバータ用小型の適応型スロープ補償回路,電子情報通信学会A論文誌, J93-A, 1, 27-30 (2010).CiNii
  30. Socheat Heng and Cong-Kha Pham: A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator, IEICE Trans. Electronics, E92-C, 9, 1208-1214 (2009).J-STAGE
  31. ヘイン　ソチェット, 範 公可: シリーズレギュレータが高速起動可能な突入電流制限回路の構成,電子情報通信学会A論文誌, J92-A, 7, 521-523 (2009).
  32. ヘイン　ソチェット, 範 公可: 低消費電力シリーズレギュレータ用の負荷過渡応答の高速化回路, 電子情報通信学会A論文誌, J92-A, 7, 470-476 (2009).CiNii
  33. 柴田 公男, 範 公可: 高精度アクティブ分圧回路,電子情報通信学会A論文誌, J91-A, 9, 919-922 (2008).CiNii
  34. 原田 津, 範 公可: 高速かつ低消費電力な全加算器,電子情報通信学会A論文誌, J91-A, 9, 915-918 (2008).CiNii
  35. ヘイン　ソチェット, 範 公可: シリーズレギュレータの低消費電力化による電源電圧のリプル除去率(PSRR)の劣化の改善,電子情報通信学会A論文誌, J91-A, 4, 535-537 (2008).CiNii
  36. ヘイン　ソチェット, 範 公可: ボンディングワイヤの抵抗を考慮したシリーズレギュレータの負荷安定のための補正回路, 電子情報通信学会A論文誌, J91-A, 1, 172-175 (2008).CiNii
  37. 範 公可: コンパクトなハミング重み比較回路, 電子情報通信学会A論文誌, J90-A, 10, 762-766 (2007).CiNii
  38. 範 公可, 高橋　俊太郎: 最適設計による高速かつ小規模なディジタル比較回路, 電子情報通信学会A論文誌, J90-A, 9, 727-730 (2007).CiNii
  39. ヘイン　ソチェット, 清水　麻里江, 範 公可: 低消費電力シリーズレギュレータ用の過電流保護回路,電子情報通信学会A論文誌, J90-A, 7, 619-621 (2007).CiNii
  40. Cong-Kha Pham and Watarru Noguchi: Solving Large N-Queen Problem with a Maximum Neuron Model by Canceling Diagonal Competition, Journal of Signal Processing, 11, 1, 25-32 (2007).
  41. Socheat Heng and Cong-Kha Pham: Low Power Full Input Range Current-Mode Operational Amplifier Using Level Shifter Technique, Journal of Signal Processing, 10, 6, 385-390 (2006).CiNii
  42. 野口 渉, 範 公可: マキシマムニューロン及び修正Hill-Climbing項を用いたN-Queen問題の解法, 電子情報通信学会A論文誌, J89-A, 11, 1012-1017 (2006).CiNii
  43. 柳沢 真, 範 公可:低消費電力全加算器, 電子情報通信学会A論文誌, J88-A, 10, 1163-1167 (2005).CiNii
  44. Cong-Kha Pham and Makoto Fukuda: A Stochastic Bit-Stream Digital Neuron Using Generalized LFSR and Its Application to Two-Dimensional Binary Classification, Journal of Signal Processing, 9, 5, 409-414 (2005).CiNii
  45. 東 裕貴，範 公可: 並列Generalized-LFSRを用いた自己組み込みテスト, 電子情報通信学会A論文誌, J87-A, 9, 1252-1253 (2004).
  46. Cong-Kha Pham: Implementation of a Novel CMOS Synapses Circuit, Journal of Signal Processing, 7, 1, 111-116 (2003).
  47. 範　公可: 新型CMOSシナプス回路, 電子情報通信学会A論文誌, J84-A, 2, 246-248 (2001).CiNii
  48. Cong-Kha Pham: A Neural-Based A/D Converter Using only CMOS Inverter, Journal of Signal Processing, 4, 1, 95-98 (2000).
  49. Cong-Kha Pham: Bifurcational Communication with Novel Chaotic Transistors Circuit, International Journal of Chaos Theory and Applications, 2, 2, 25-34 (1997).
  50. Cong-Kha Pham, M. Korehisa and M. Tanaka: Chaotic Behavior and Synchronization Phenomena in A Novel Chaotic Transistors Circuit, IEEE Trans. Circuit and Systems, I: Fundamental Theory and Applications, 43, 12, 1006-1011 (1996).IEEE
  51. Cong-Kha Pham, M. Ikegami and M. Tanaka: Discrete Time Cellular Neural Networks with Two Types of Neuron Circuits for Image Coding and Their VLSI Implementation, IEICE Trans. Fundamentals, E-78-A, 8, 291-299 (1995).
  52. Cong-Kha Pham, M. Tanaka and K. Shono: Chaotic Behavior in Simple looped MOS Inverters, IEICE Trans. Fundamentals, E-78-A, 3, 291-299 (1995).CiNii
  53. Cong-Kha Pham, M. Tanaka and K. Shono: A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System: IEICE Trans. Fundamentals, E-76-A, 10, 1684-1693 (1993).CiNii
  54. Cong-Kha Pham and K. Shono: A CMOS Cell Compiler for a Bit-Mapping CAD System, IEICE Trans. Fundamentals, E-74, 9, 2603-2611 (1991).
  55. 高窪　統，ファム・コン・カー，庄野克房: 領域アクセスを行なうビットマップメモリバンク”電子情報通信学会C-II論文誌, J75-C-II, 4, 227-235 (1991).CiNii

 

更新者: Lê Anh Tiến | 日にち: 02 May 2024 Time: 17:16:34